Guidelines for the Power Constrained Design of a CMOS Tuned LNA

The first stage of a receiver is typically an LNA (Low Noise Amplifier) which needs to provide sufficient gain while introducing as little noise as possible. The classical noise optimization technique for LNA design presumes that a device is given with fixed characteristics, and thus offers no explicit guidance on how to best exercise the IC designer’s freedom in tailoring device geometries [1]. Recently proposed noise optimization techniques for CMOS RF circuits permit greater flexibility in selection of device geometries as well as matching elements and biasing conditions to minimize the noise figure for a specified gain or power dissipation [1]. Nevertheless such approaches still have ambiguity because intrinsic noise is assumed to be biasindependent. To utilize the new degrees of freedom in noise figure optimization, more complete intrinsic noise information of MOSFETs across the entire bias range is needed. A recent study has reported extensive experimental noise results of the 0.75 μm SOI MOSFET technology [2] but it provided limited guidance for actual LNA design. A physical noise simulator has been developed using twodimensional device simulation; successful noise simulation results have been reported for MOSFETs with channel lengths down to 0.25 μm for the first time [3]. Based on intrinsic high frequency noise simulation results, this paper presents explicit design guidelines for a CMOS tuned LNA with power constraints.